{"id":407,"date":"2025-12-02T16:32:35","date_gmt":"2025-12-02T08:32:35","guid":{"rendered":"https:\/\/www.52runoob.com\/?p=407"},"modified":"2025-12-02T16:32:35","modified_gmt":"2025-12-02T08:32:35","slug":"vivado%e8%bf%9b%e9%98%b6-19p%e7%9a%84%e6%97%b6%e9%92%9f%e8%b5%84%e6%ba%90%e7%bd%91%e7%bb%9c%e5%92%8cclock_dedicated_route%e7%9a%84%e5%ba%94%e7%94%a8","status":"publish","type":"post","link":"https:\/\/www.52runoob.com\/index.php\/2025\/12\/02\/vivado%e8%bf%9b%e9%98%b6-19p%e7%9a%84%e6%97%b6%e9%92%9f%e8%b5%84%e6%ba%90%e7%bd%91%e7%bb%9c%e5%92%8cclock_dedicated_route%e7%9a%84%e5%ba%94%e7%94%a8\/","title":{"rendered":"Vivado\u8fdb\u9636-19P\u7684\u65f6\u949f\u8d44\u6e90\u7f51\u7edc\u548cCLOCK_DEDICATED_ROUTE\u7684\u5e94\u7528"},"content":{"rendered":"\n

\u4e0b\u9762\u7ed9\u4f60\u4e00\u4efd\u66f4 \u7cbe\u51c6\u8d34\u5408\u201cVivado \u8fdb\u9636 – 19P \u65f6\u949f\u8d44\u6e90\u7f51\u7edc\u4e0e CLOCK_DEDICATED_ROUTE \u5e94\u7528\u201d<\/strong> \u7684\u5b8c\u6574\u6280\u672f\u8bb2\u89e3\uff08\u5de5\u7a0b\u5e08\u89c6\u89d2 + \u5b9e\u6218\u53ef\u7528\uff09\u3002<\/p>\n\n\n\n

\n\n\n\n

\u2b50 \u4e3a\u4ec0\u4e48\u8d44\u6599\u4e2d\u5e38\u8bf4\u201c19P \u7684\u65f6\u949f\u8d44\u6e90\u7f51\u7edc\u95ee\u9898\u201d\uff1f<\/h1>\n\n\n\n

\u5728 Vivado \u7684 placement\uff08\u5e03\u5c40\uff09\u9636\u6bb5\uff0c\u4f1a\u51fa\u73b0\u5982\u4e0b Category\uff1a<\/p>\n\n\n

\n[Place 19-xxxx] &lt;clock-name> is not routed on a global clock resource\n\n<\/pre><\/div>\n\n\n
\u56e0\u6b64\u5de5\u7a0b\u5e08\u53e3\u4e2d\u5e38\u8bf4 \u201c19P\u201d \u6216 \u201c19 \u7c7b\u62a5\u9519\/\u8b66\u544a\u201d\u3002<\/p>\n\n\n\n
19 \u7cfb\u5217\u62a5\u9519\u5747\u4e0e\u65f6\u949f\u8d44\u6e90\uff08Clocking Resources\uff09\u76f4\u63a5\u76f8\u5173\u3002<\/strong><\/p>\n\n\n\n
\n\n\n\n
1\ufe0f\u20e3 Vivado \u65f6\u949f\u8d44\u6e90\u7f51\u7edc\u57fa\u7840\uff08\u5fc5\u987b\u638c\u63e1\uff09<\/h1>\n\n\n\n
Xilinx FPGA \u5185\u65f6\u949f\u8d44\u6e90\u5206 4 \u5c42\uff1a<\/p>\n\n\n\n
\u5c42\u7ea7<\/th>\u8d44\u6e90<\/th>\u6548\u679c<\/th><\/tr><\/thead>
\u2460 \u5168\u5c40\u5c42<\/td>BUFG \/ BUFGCE \/ BUFGCTRL<\/td>\u8de8\u5168\u82af\u7247\u3001\u5ef6\u8fdf\u6700\u4f4e<\/td><\/tr>
\u2461 \u533a\u57df\u5c42<\/td>BUFH \/ BUFHCE<\/td>\u5355\u4e2a Clock Region<\/td><\/tr>
\u2462 \u5782\u76f4 Spine<\/td>Vertical Clock Backbone<\/td>\u591a\u533a\u57df\u8fde\u901a<\/td><\/tr>
\u2463 \u666e\u901a\u5e03\u7ebf<\/td>Fabric Routing<\/td>\u4e0d\u53ef\u7528\u4e8e\u65f6\u949f\uff01<\/strong>\uff08\u4f1a\u89e6\u53d1 19P\uff09<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n
\u26a0 \u6838\u5fc3\uff1a\u65f6\u949f\u5fc5\u987b\u8d70\u4e13\u7528\u7f51\u7edc\uff08BUFG \u2192 Global Clock Network\uff09<\/strong>\u3002<\/p>\n\n\n\n
\n\n\n\n
2\ufe0f\u20e3 \u5178\u578b\u7684\u201c19P\u201d \u62a5\u9519\u5b9e\u4f8b\uff08\u4f60\u5927\u6982\u7387\u89c1\u8fc7\uff09<\/h1>\n\n\n\n
\ud83d\udd25 \u62a5\u9519\u793a\u4f8b 1\uff1a<\/h3>\n\n\n
\n[Place 19-329] The net &lt;clk_x> is not routed on a global clock net.\n\n<\/pre><\/div>\n\n\n
\ud83d\udd25 \u62a5\u9519\u793a\u4f8b 2\uff1a<\/h3>\n\n\n
\n[Place 30-574] CLOCK_DEDICATED_ROUTE required but not allowed\n\n<\/pre><\/div>\n\n\n
\ud83d\udd25 \u62a5\u9519\u793a\u4f8b 3\uff1a<\/h3>\n\n\n
\n[Place 19-345] Clock &lt;mmcm_clkout0> drives logic in multiple clock regions via fabric routing.\n\n<\/pre><\/div>\n\n\n
\u8fd9\u4e9b\u672c\u8d28\u4e0a\u90fd\u662f\uff1a<\/p>\n\n\n\n
\n
\u65f6\u949f\u5e94\u8d70 \u4e13\u7528\u65f6\u949f\u7f51\u7edc<\/strong>\uff0c\u4f46 Vivado \u53d1\u73b0\u4f60\u8d70\u7684\u662f \u666e\u901a\u5e03\u7ebf<\/em> \u6216 \u8de8\u533a\u4e0d\u5408\u6cd5\u5e03\u7ebf<\/em>\u3002<\/p>\n<\/blockquote>\n\n\n\n
\n\n\n\n
3\ufe0f\u20e3 \u4e3a\u4ec0\u4e48\u4f1a\u51fa\u73b0 19P\uff1f<\/h1>\n\n\n\n
\u6700\u5e38\u89c1 5 \u4e2a\u539f\u56e0\u5982\u4e0b\uff1a<\/p>\n\n\n\n
\n\n\n\n
\u2714 \u2460 \u65f6\u949f\u6ca1\u6709\u7ecf\u8fc7 BUFG\uff08\u6700\u5e38\u89c1\uff09<\/h2>\n\n\n\n
\u4f8b\u5982\uff1a<\/p>\n\n\n
\nassign clk2 = clk1;\n\n<\/pre><\/div>\n\n\n
Vivado \u4f1a\u628a clk2 \u770b\u6210\u666e\u901a\u4fe1\u53f7\u3002<\/p>\n\n\n\n
\u89e6\u53d1 19-329 \/ CLOCK_DEDICATED_ROUTE \u62a5\u9519\u3002<\/p>\n\n\n\n
\n\n\n\n
\u2714 \u2461 BUFR \/ BUFH \u533a\u57df\u65f6\u949f\u8de8\u591a\u4e2a\u533a\u57df\u4f7f\u7528<\/h2>\n\n\n\n
\u4f8b\u5982\u4f60\u7528 BUFR \u751f\u6210\u4e00\u4e2a\u65f6\u949f\uff0c\u4f46\u9a71\u52a8\u4e86\u591a\u4e2a Clock Region \u2192 \u8fdd\u89c4\u3002<\/p>\n\n\n\n
\n\n\n\n
\u2714 \u2462 MMCM\/PLL \u7684\u8f93\u51fa\u672a\u8fde\u63a5\u5230 BUFG<\/h2>\n\n\n\n
MMCM\/PLL \u7684 O \u8f93\u51fa\u6ca1\u6709\u7528 BUFG \u4f1a\u76f4\u63a5\u89e6\u53d1 19P\u3002<\/p>\n\n\n\n
\n\n\n\n
\u2714 \u2463 \u65f6\u949f\u4f5c\u4e3a\u4fe1\u53f7\u903b\u8f91\u7ec4\u5408\u4e0d\u5408\u6cd5\u4f7f\u7528<\/h2>\n\n\n\n
\u4f8b\u5982\uff1a<\/p>\n\n\n
\nalways @(posedge clk_in or posedge rst)  \/\/ \u5408\u6cd5\nalways @(posedge some_logic_signal)      \/\/ \u975e\u6cd5\uff0c\u4f1a\u89e6\u53d1 19P\n\n<\/pre><\/div>\n\n\n
\n\n\n\n
\u2714 \u2464 Pblock \u9650\u5236\u5bfc\u81f4\u65f6\u949f\u65e0\u6cd5\u8de8\u533a\u8def\u7531<\/h2>\n\n\n\n
\u4f60\u628a\u903b\u8f91\u6846\u5728\u67d0\u4e2a Pblock \u4e2d\uff0c\u4f46\u65f6\u949f\u6765\u6e90\u4e0d\u5728\u8be5\u533a\u57df\uff0c\u5bfc\u81f4 Vivado \u65e0\u6cd5\u4f7f\u7528\u4e13\u7528 Spine \u7ed3\u6784\u3002<\/p>\n\n\n\n
\n\n\n\n
4\ufe0f\u20e3 CLOCK_DEDICATED_ROUTE \u5c5e\u6027\u8be6\u89e3<\/h1>\n\n\n\n
Vivado \u9ed8\u8ba4\u8981\u6c42\uff1a<\/p>\n\n\n
\nCLOCK_DEDICATED_ROUTE = TRUE\n\n<\/pre><\/div>\n\n\n
\u5373\uff1a
\u2714 \u4f7f\u7528\u5168\u5c40\u65f6\u949f\u7f51\u7edc
\u2714 \u4e0d\u5141\u8bb8\u4f7f\u7528\u666e\u901a\u5e03\u7ebf\uff08fabric routing\uff09<\/p>\n\n\n\n
\u5f53\u4f60\u8bbe\u7f6e\u4e0b\u9762\u8fd9\u6761\u65f6\uff1a<\/p>\n\n\n
\nset_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_test]\n\n<\/pre><\/div>\n\n\n
Vivado \u4f1a\u5141\u8bb8\u4f60\u8d70\u666e\u901a\u5e03\u7ebf\uff0c\u4f46\u4f1a\u8b66\u544a\u4f60\u53ef\u80fd\uff1a<\/p>\n\n\n\n